View FM18L08-70-P_1738610.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

n o t r e c o mm e n d e d f o r n e w d e s i g n s a l t e r n at i v e : f m 2 8 v 0 2 0 this product conforms to specifications per the terms of the ramtron ramtron international corporation standard warranty. the product has completed ramtron?s internal 1850 ramtron drive, colorado springs, co 80921 qualification testing and has reached production status. (800) 545-fram, (719) 481-7000 http://www.ramtron.com rev. 3.5 sept. 2009 1 of 13 fm18l08 256kb bytewide fram memory features 256k bit ferroelectric nonvolatile ram ? organized as 32,768 x 8 bits ? 45 year data retention ? unlimited read/write cycles ? nodelay? writes ? advanced high-reliability ferroelectric process superior to battery-backed sram ? no battery concerns ? monolithic reliability ? true surface mount solution, no rework steps ? superior for moisture, shock, and vibration ? resistant to negative voltage undershoots sram & eeprom compatible ? jedec 32kx8 sram & eeprom pinout ? 70 ns access time ? 140 ns cycle time low power operation ? 3.0v to 3.65v operation ? 15 ma active current ? 15 a standby current industry standard configuration ? industrial temperature -40 c to +85 c ? 32-pin ?green? tsop package ? 28-pin soic or dip package ? ?green? packaging options description the fm18l08 is a 256-kilobit nonvolatile memory employing an advanced ferroelectric process. a ferroelectric random access memory or fram is nonvolatile and reads and writes like a ram. it provides data retention for 45 years while eliminating the reliability concerns, functional disadvantages and system design complexities of battery-backed sram (bbsram). fast write timing and high write endurance make fram superior to other types of nonvolatile memory. in-system operation of the fm18l08 is very similar to other ram based devices. read cycle and write cycle times are equal. the fram memory, however, is nonvolatile due to its unique ferroelectric memory process. unlike bbsram, the fm18l08 is a truly monolithic nonvolatile memory. it provides the same functional benefits of a fast write without the disadvantages associated with modules and batteries or hybrid memory solutions. these capabilities make the fm18l08 ideal for nonvolatile memory applications requiring frequent or rapid writes in a bytewide environment. the availability of a surface-mount package improves the manufacturability of new designs, while the dip package facilitates simple design retrofits. device specifications are guaranteed over a temperature range of -40c to +85c. pin configurations ordering information fm18l08-70-tg * 70 ns access, 32-pin ?green? tsop fm18l08-70-s * 70 ns access, 28-pin soic FM18L08-70-P * 70 ns access, 28-pin dip fm18l08-70-sg * 70 ns access, 28-pin ?green? soic FM18L08-70-Pg * 70 ns access, 28-pin ?green? dip * end of life. last time buy nov. 2009. tsop-i 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 nc oe a11 a9 a8 a13 we vdd a14 a12 a7 a6 a5 a4 a3 nc 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 nc a10 ce dq7 dq6 dq5 dq4 dq3 vss dq2 dq1 dq0 a0 a1 a2 nc
n o t r e c o mm e n d e d f o r n e w d e s i g n s a l t e r n at i v e : f m 2 8 v 0 2 0 fm18l08 rev. 3.5 sept. 2009 2 of 13 address latch a0-a14 ce control logic we row decoder block decoder column decoder a0-a7 a8-a9 a10-a14 i/o latch bus driver oe 32,768 x 8 fram array dq0-7 figure 1. block diagram pin description pin name type pin description a0-a14 input address: the 15 address lines select one of 32,768 bytes in the fram array. the address value is latched on the falling edge of /ce. dq0-7 i/o data: 8-bit bi-directional data bus for accessing the fram array. /ce input chip enable. /ce selects the device when low. asserting /ce low causes the address to be latched internally. address changes that occur after /ce goes low will be ignored until the next falling edge occurs. /oe input output enable: asserting /oe low causes the fm18l08 to drive the data bus when valid data is available. deasserting /oe high causes the dq pins to be tri-stated. /we input write enable: asserting /we low causes the fm18l08 to write the contents of the data bus to the address location latched by the falling edge of /ce. vdd supply supply voltage vss supply ground functional truth table /ce /we function h x standby/precharge x latch address (and begin write if /we=low) l h read l write note: the /oe pin controls only the dq output buffers.
n o t r e c o mm e n d e d f o r n e w d e s i g n s a l t e r n at i v e : f m 2 8 v 0 2 0 fm18l08 rev. 3.5 sept. 2009 3 of 13 overview the fm18l08 is a bytewide fram memory. the memory array is logically organized as 32,768 x 8 and is accessed using an industry standard parallel interface. all data written to the part is immediately nonvolatile with no delay. functional operation of the fram memory is the same as sram type devices, except the fm18l08 requires a falling edge of /ce to start each memory cycle. memory operation users access 32,768 memory locations each with 8 data bits through a parallel interface. the cycle time is the same for read and write memory operations. this simplifies memory controller logic and timing circuits. likewise the access time is the same for read and write memory operations. when /ce is deasserted high, a precharge operation begins, and is required of every memory cycle. thus unlike sram, the access and cycle times are not equal. writes occur immediately at the end of the access with no delay. unlike an eeprom, it is not necessary to poll the device for a ready condition since writes occur at bus speed. note that the fm18l08 contains a limited low voltage write protection circuit. this will prevent access when v dd is much lower than the specified operating range. it is still the user?s responsibility to ensure that v dd is within data sheet tolerances to prevent incorrect operation. the fm18l08 is designed to operate in a manner similar to other bytewide memory products. for users familiar with sram, the performance is comparable but the bytewide interface operates in a slightly different manner as described below. for users familiar with eeprom, the obvious differences result from the higher write performance of fram technology including nodelay writes and from unlimited write endurance. read operation a read operation begins on the falling edge of /ce. at this time, the address bits are latched and a memory cycle is initiated. once started, a full memory cycle must be completed internally regardless of the state of /ce. data becomes available on the bus after the access time has been satisfied. after the address has been latched, the address value may be changed upon satisfying the hold time parameter. unlike an sram, changing address values will have no effect on the memory operation after the address is latched. the fm18l08 drives the data bus when /oe is asserted to a low state. if /oe is asserted after the memory access time has been satisfied, the data bus will be driven with valid data. if /oe is asserted prior to completion of the memory access, the data bus will be driven when valid data is available. this feature minimizes supply current in the system by eliminating transients caused by invalid data being driven onto the bus. when /oe is inactive the data bus will remain tri-stated. write operation writes operations require the same time as reads. the fm18l08 supports both /ce- and /we-controlled write cycles. in all cases, the address is latched on the falling edge of /ce. in a /ce-controlled write, the /we signal is asserted prior to beginning the memory cycle. that is, /we is low when /ce falls. in this case, the device begins the memory cycle as a write. the fm18l08 will not drive the data bus regardless of the state of /oe. in a /we-controlled write, the memory cycle begins on the falling edge of /ce. the /we signal falls after the falling edge of /ce. therefore, the memory cycle begins as a read. the data bus will be driven according to the state of /oe until /we falls. the timing of both /ce- and /we-controlled write cycles is shown in the electrical specifications. write access to the array begins asynchronously after the memory cycle is initiated. the write access terminates on the rising edge of /we or /ce, whichever is first. data set-up time, as shown in the electrical specifications, indicates the interval during which data cannot change prior to the end of the write access. unlike other truly nonvolatile memory technologies, there is no write delay with fram. since the read and write access times of the underlying memory are the same, the user experiences no delay through the bus. the entire memory operation occurs in a single bus cycle. therefore, any operation including read or write can occur immediately following a write. data polling, a technique used with eeproms to determine if a write is complete, is unnecessary. precharge operation the precharge operation is an internal condition where the state of the memory is prepared for a new access. all memory cycles consist of a memory access and a precharge. the precharge is user initiated by taking the /ce signal high or inactive. it
n o t r e c o mm e n d e d f o r n e w d e s i g n s a l t e r n at i v e : f m 2 8 v 0 2 0 fm18l08 rev. 3.5 sept. 2009 4 of 13 must remain high for at least the minimum precharge timing specification. the user dictates the beginning of this operation since a precharge will not begin until /ce rises. however, the device has a maximum /ce low time specification that must be satisfied. fram design considerations when designing with fram for the first time, users of sram will recognize a few minor differences. first, bytewide fram memories latch each address on the falling edge of chip enable. this allows the address bus to change after starting the memory access. since every access latches the memory address on the falling edge of /ce, users cannot ground it as they might with sram. users who are modifying existing designs to use fram should examine the memory controller for timing compatibility of address and control pins. each memory access must be qualified with a low transition of /ce. in many cases, this is the only change required. an example of the signal relationships is shown in figure 2 below. also shown is a common sram signal relationship that will not work for the fm18l08. the reason for /ce to strobe for each address is two- fold: it latches the new address and creates the necessary precharge period while /ce is high. address 1 address 2 data 1 data 2 valid memory signaling relationship ce address data fram signaling address 2 data 1 ce address data sram signaling invalid memory signaling relationship address 1 data 2 figure 2. memory address relationships
n o t r e c o mm e n d e d f o r n e w d e s i g n s a l t e r n at i v e : f m 2 8 v 0 2 0 fm18l08 rev. 3.5 sept. 2009 5 of 13 a second design consideration relates to the level of v dd during operation. battery-backed srams are forced to monitor v dd in order to switch to battery backup. they typically block user access below a certain v dd level in order to prevent loading the battery with current demand from an active sram. the user can be abruptly cut off from access to the memory in a power down situation without warning. fram memories do not need this system overhead. the memory will not block access at any v dd level. the user, however, should prevent the processor from accessing memory when v dd is out-of-tolerance. the common design practice of holding a processor in reset during powerdown may be sufficient. it is recommended that chip enable is pulled high and allowed to track v dd during powerup and powerdown cycles. it is the user?s responsibility to ensure that chip enable is high to prevent accesses below v dd min. (3.0v). figure 3 shows an external pullup resistor on /ce which will keep the pin high during power cycles assuming the mcu/mpu pin tri-states during the reset condition. the pullup resistor value should be chosen to ensure the /ce pin tracks v dd yet a high enough value that the current drawn when /ce is low is not an issue. figure 3. use of pullup resistor on /ce ce we oe a(14:0) dq fm18l08 v dd mcu/ mpu r
n o t r e c o mm e n d e d f o r n e w d e s i g n s a l t e r n at i v e : f m 2 8 v 0 2 0 fm18l08 rev. 3.5 sept. 2009 6 of 13 electrical specifications absolute maximum ratings symbol description ratings v dd power supply voltage with respect to v ss -1.0v to +5.0v v in voltage on any signal pin with respect to v ss -1.0v to +5.0v and v in < v dd +1v t stg storage temperature -55 c to +125 c t lead lead temperature (soldering, 10 seconds) 300 c v esd electrostatic discharge voltage - human body model (jedec std jesd22-a114-b) - machine model (jedec std jesd22-a115-a) 4kv 400v package moisture sensitivity level msl-1 (soic/dip) msl-2 (tsop) stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only, and the functional operation of the device at these or any other conditions above those listed in the operational section of this specification is not implied. exposure to absolute maximum ratings conditions for extended periods may affect device reliabilit y. dc operating conditions (t a = -40 c to + 85 c, v dd = 3.0v to 3.65v) symbol parameter min typ max units notes v dd power supply 3.0 3.65 v i dd v dd supply current ? active - 7 15 ma 1 i sb1 standby current ? ttl 400 a 2 i sb2 standby current ? cmos 7 15 a 3 i li input leakage current - 10 a 4 i lo output leakage current - 10 a 4 v ih input high voltage 2.0 v dd + 0.5 v v il input low voltage -0.5 0.8 v v oh output high voltage ( i oh = -1.0 ma) 2.4 - v v ol output low voltage ( i ol = 3.2 ma) - 0.4 v notes 1. v dd = 3.65v, /ce cycling at minimum cycle time. all inputs at cmos levels, all outputs unloaded. 2. v dd = 3.65v, /ce at v ih , all other pins at ttl levels. 3. v dd = 3.65v, /ce at v dd , all other pins at cmos levels. 4. v in , v out between v dd and v ss .
n o t r e c o mm e n d e d f o r n e w d e s i g n s a l t e r n at i v e : f m 2 8 v 0 2 0 fm18l08 rev. 3.5 sept. 2009 7 of 13 read cycle ac parameters (t a = -40 c to + 85 c, v dd = 3.0v to 3.65v) symbol parameter min max units notes t ce chip enable access time ( to data valid) 70 ns t c a chip enable active time 70 2,000 ns t rc read cycle time 140 ns t pc precharge time 70 ns t as address setup time 0 ns t ah address hold time 15 ns t oe output enable access time 10 ns t hz chip enable to output high-z 15 ns 1 t ohz output enable to output high-z 15 ns 1 write cycle ac parameters (t a = -40 c to + 85 c, v dd = 3.0v to 3.65v) symbol parameter min max units notes t c a chip enable active time 70 2,000 ns t cw chip enable to write high 70 ns t wc write cycle time 140 ns t pc precharge time 70 ns t as address setup time 0 ns t ah address hold time 15 ns t wp write enable pulse width 40 ns t ds data setup 40 ns t dh data hold 0 ns t wz write enable low to output high z 15 ns 1 t wx write enable high to output driven 10 ns 1 t hz chip enable to output high-z 15 ns 1 t ws write setup 0 ns 2 t wh write hold 0 ns 2 notes 1 this parameter is periodically sampled and not 100% tested. 2 the relationship between /ce and /we determines if a /ce- or /we-controlled write occurs. there is no timing specification associated with this relationship. data retention (v dd = 3.0v to 3.65v) parameter min units notes data retention 45 years 1 power cycle timing (t a = -40 c to + 85 c, v dd = 3.0v to 3.65v) symbol parameter min units notes t pu v dd (min.) to first access start 1 s t pd last access complete to v dd (min.) 0 s capacitance (t a = 25 c , f=1 mhz, v dd = 3.3v) symbol parameter max units notes c i/o input/output capacitance (dq) 8 pf c in input capacitance 6 pf
n o t r e c o mm e n d e d f o r n e w d e s i g n s a l t e r n at i v e : f m 2 8 v 0 2 0 fm18l08 rev. 3.5 sept. 2009 8 of 13 ac test conditions input pulse levels 0.1 v dd to 0.9 v dd input rise and fall times 5 ns input and output timing levels 1.5v read cycle timing ce a0-14 oe dq0-7 t as t ah t ce t oe t ca t rc t pc t ohz t hz write cycle timing - /ce controlled timing ce a0-14 we dq0-7 t as t ah t ca t wc t pc oe t ws t ds t dh t wh equivalent ac load circuit 1.3v output 3300 ? 50 pf
n o t r e c o mm e n d e d f o r n e w d e s i g n s a l t e r n at i v e : f m 2 8 v 0 2 0 fm18l08 rev. 3.5 sept. 2009 9 of 13 write cycle timing - /we controlled timing ce a0-14 we dq0-7 out t as t ah t ca t wc t pc oe t ws t wh dq0-7 in t ds t wp t wz t wx t dh t c w power cycle timing vdd min vdd min t pc t pd t pu vdd ce
n o t r e c o mm e n d e d f o r n e w d e s i g n s a l t e r n at i v e : f m 2 8 v 0 2 0 fm18l08 rev. 3.5 sept. 2009 10 of 13 mechanical drawing 28-pin soic (jedec ms-013d variation ae) all dimensions in millimeters pin 1 7.50 0.10 10.30 0.30 17.90 0.20 0.10 0.30 2.35 2.65 0.33 0.51 1.27 typ 0.10 0.25 0.75 45 0.40 1.27 0.23 0.32 0? - 8? soic package marking scheme legend: xxxx= part number, s=speed (-70), p= package type (-sg) r=rev code, yy=year, ww=work week, llllll= lot code example: fm18l08, 70ns speed, ?green? soic package, b rev., year 2006, work week 30, lot code 50013g ramtron fm18l08-70-sg b063050013g ramtron xxxxxxx-s-p ryywwlllllll
n o t r e c o mm e n d e d f o r n e w d e s i g n s a l t e r n at i v e : f m 2 8 v 0 2 0 fm18l08 rev. 3.5 sept. 2009 11 of 13 28-pin 600-mil dip (jedec ms-011) all dimensions in inches 0.485 0.580 1.380 1.565 0.015 min. 0.100 bsc 0.005 min. 0.125 0.195 0.250 max 0.600 bsc 0.700 max. 0.600 0.625 0.030 0.070 pin 1 0.014 0.022 0.115 0.200 dip package marking scheme legend: xxxx= part number, s=speed (-70), p= package type (-pg) r=rev code, yy=year, ww=work week, llllll= lot code example: fm18l08, 70ns speed, ?green? dip package, b rev., year 2006, work week 30, lot code 50013g ramtron FM18L08-70-Pg b063050013g ramtron xxxxxxx-s-p ryywwlllllll
n o t r e c o mm e n d e d f o r n e w d e s i g n s a l t e r n at i v e : f m 2 8 v 0 2 0 fm18l08 rev. 3.5 sept. 2009 12 of 13 32-pin shrunk tsop-i (8.0 x 13.4 mm) all dimensions in millimeters tsop package marking scheme legend: xxxxxx= part number, sp= speed/package (-70tg) r=rev code, yy=year, ww=work week, llllll= lot code example: fm18l08-70-tg, ?green? tsop package, b rev., year 2006, work week 51, lot 60012t2 ramtron fm18l08-70tg b065160012t2 ramtron xxxxxxx-sp yywwllllll
n o t r e c o mm e n d e d f o r n e w d e s i g n s a l t e r n at i v e : f m 2 8 v 0 2 0 fm18l08 rev. 3.5 sept. 2009 13 of 13 revision history revision date summary 0.1 3/23/01 initial release 0.2 9/28/01 changed data retention table. modified temperature range to commercial. 0.3 3/18/02 changed temperature range to industrial and vdd range to 3v ? 3.65v. changed precharge time to 70ns. added note for 2.7v operation. updated package drawings. 1.0 6/15/02 updated to preliminary status, changed storage temperature. 2.0 12/10/02 updated to production status, removed ref to 2.7v operation. 2.1 5/1/03 changed tca (max) value. reworded notes 2 and 3 in dc operating conditions table. 2.2 7/14/04 added ?green? packaging options. 3.0 6/12/06 added esd and package msl ratings. updated rev numbering and footer. added recommendation on ce pin during power cycles. 3.1 11/27/06 added tsop packaging option. 3.2 2/20/07 updated tsop msl rating. 3.3 5/15/07 redraw package outlines, added marking scheme to soic/dip. 3.4 7/30/07 extended data retention to 45 years based on recent test results. 3.5 9/8/2009 not recommended for new designs. last time buy nov. 2009. as an alternative, use the fm28v020 device.

▲Up To Search▲

Price & Availability of FM18L08-70-P

	To Download FM18L08-70-P Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .